/*!
    \file    change log.txt
    \brief   change log for GD32VW55x firmware

    \version 2026-02-04, V1.6.0, firmware for GD32VW55x
*/

/*
    Copyright (c) 2026, GigaDevice Semiconductor Inc.

    Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

    1. Redistributions of source code must retain the above copyright notice, this
       list of conditions and the following disclaimer.
    2. Redistributions in binary form must reproduce the above copyright notice,
       this list of conditions and the following disclaimer in the documentation
       and/or other materials provided with the distribution.
    3. Neither the name of the copyright holder nor the names of its contributors
       may be used to endorse or promote products derived from this software without
       specific prior written permission.

    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
******************* V1.6.0 2026-02-04 ************************************************************************************
______________________Common______________________________________________________________________________________________
Fix file:
..\Firmware\GD32VW55x_standard_peripheral\gd32vw55x.h
fix reason:
update firmware library version get
V1.5.0:
#define __GD32VW55X_STDPERIPH_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */
V1.6.0:
#define __GD32VW55X_STDPERIPH_VERSION_SUB1   (0x06) /*!< [23:16] sub1 version */

Fix file:
..\Firmware\GD32VW55x_standard_peripheral
fix reason:
Modify the MISRA issue in Rule 14.7 that restricts each function interface to only one return statement.
include TIMER\ FWDGT\WWDGT\SPI\GPIO\EXTI\USART\DMA\HAU\PKCAU\EFUSE\CAU\RTC\QSPI\TRNG\RCU\FMC\PMU\I2C\SYSCFG\ECLIC modules.
_________________________________________________________________________________________________________________________________

______________________Module TIMER_________________________________________________________________________________________________
Fix file:
../Firmware/GD32VW55x_standard_peripheral/Source/gd32vw55x_timer.c
../Firmware/GD32VW55x_standard_peripheral/Source/gd32vw55x_timer.h

fix reason: 
Add Function: add void timer_channel_input_remap_config(uint32_t timer_periph, uint32_t remap) API.

V1.5.0:
none
V1.6.0:
/*!
    \brief      configure TIMER channel input remap
    \param[in]  timer_periph: TIMERx(x=2)
    \param[in]  remap:
                only one parameter can be selected which is shown as below:
      \arg        TIMER_IRMP_GPIO: channel 3 input is connected to GPIO
      \arg        TIMER_IRMP_IRC32K: channel 3 input is connected to IRC32K
      \arg        TIMER_IRMP_LXTAL: channel 3 input is connected to LXTAL
      \arg        TIMER_IRMP_CKOUT: channel 3 input is connected to CKOUT
    \param[out] none
    \retval     none
*/
void timer_channel_input_remap_config(uint32_t timer_periph, uint32_t remap)
{
    TIMER_IRMP(timer_periph) &= ~(uint32_t)TIMER_IRMP_CI3_RMP;
    TIMER_IRMP(timer_periph) |= remap;
}

Fix file:
../Firmware/GD32VW55x_standard_peripheral/Source/gd32vw55x_timer.c
../Firmware/GD32VW55x_standard_peripheral/Source/gd32vw55x_timer.h
../fw32103/GD32VW55x_Firmware_Library/Examples/TIMER/TIMER0_deadtime_break/main.c
/fw32103/GD32VW55x_Firmware_Library/Examples/TIMER/TIMER0_6-steps/main.c

fix reason: 
Optimize software. Fix the word spelling error：ideloffstate ->idleoffstate.

V1.5.0:
/* break parameter struct definitions */
typedef struct
{
    uint16_t runoffstate;                                    /*!< run mode off-state */
    uint32_t ideloffstate;                                   /*!< idle mode off-state */
    uint16_t deadtime;                                       /*!< dead time */
    uint16_t breakpolarity;                                  /*!< break polarity */
    uint16_t outputautostate;                                /*!< output automatic enable */
    uint16_t protectmode;                                    /*!< complementary register protect control */
    uint16_t breakstate;                                     /*!< break enable */
}timer_break_parameter_struct;
V1.6.0:
/* break parameter struct definitions */
typedef struct
{
    uint16_t runoffstate;                                    /*!< run mode off-state */
    uint32_t idleoffstate;                                   /*!< idle mode off-state */
    uint16_t deadtime;                                       /*!< dead time */
    uint16_t breakpolarity;                                  /*!< break polarity */
    uint16_t outputautostate;                                /*!< output automatic enable */
    uint16_t protectmode;                                    /*!< complementary register protect control */
    uint16_t breakstate;                                     /*!< break enable */
}timer_break_parameter_struct;

_________________________________________________________________________________________________________________________________

______________________Module PMU_________________________________________________________________________________________________
Fix file:
/fw32103/GD32VW55x_Firmware_Library/Examples/PMU/Deepsleep_wakeup_RTC/main.c
/fw32103/GD32VW55x_Firmware_Library/Examples/PMU/Deepsleep_wakeup_exti/main.c
/fw32103/GD32VW55x_Firmware_Library/Examples/PMU/Standby_wakeup_RTC/main.c
/fw32103/GD32VW55x_Firmware_Library/Examples/PMU/Standby_wakeup_pin/main.c

fix reason:
Bug fix. Prevent Vcore fluctuations caused by frequency switching.
V1.5.0:
 none
V1.6.0:
/* software delay to prevent the impact of Vcore fluctuations.
   It is strongly recommended to include it to avoid issues caused by self-removal. */
static void _soft_delay_(uint32_t time)
{
    __IO uint32_t i;
    for(i=0; i<time*10; i++){
    }
}

V1.5.0:
    while(1){
        delay_1ms(50U);
        /* PMU enters deepsleep mode */
        pmu_to_deepsleepmode(PMU_LDO_LOWPOWER,PMU_LOWDRIVER_ENABLE, WFI_CMD);
        gd_eval_led_toggle(LED1);
    }
V1.6.0:
    while(1){
        delay_1ms(50U);
        /* The following is to prevent Vcore fluctuations caused by frequency switching. 
            It is strongly recommended to include it to avoid issues caused by self-removal. */
        rcu_ahb_clock_config(RCU_AHB_CKSYS_DIV2);
        _soft_delay_(0x50);
        rcu_ahb_clock_config(RCU_AHB_CKSYS_DIV4);
        _soft_delay_(0x50);
        /* PMU enters deepsleep mode */
        pmu_to_deepsleepmode(PMU_LDO_LOWPOWER,PMU_LOWDRIVER_ENABLE, WFI_CMD);
        gd_eval_led_toggle(LED1);
    }

_________________________________________________________________________________________________________________________________

______________________Module FMC_________________________________________________________________________________________________
Fix file:
/fw32103/GD32VW55x_Firmware_Library/Examples/FMC/Erase_Program/main.c
/fw32103/GD32VW55x_Firmware_Library/Examples/FMC/Read_offset_region/main.c

fix reason:
Optimize software. Add flags clear opreation before erase/program opreation.
V1.5.0:
void fmc_program(void)
{
    /* unlock the flash program/erase controller */
    fmc_unlock();

    address = FMC_WRITE_START_ADDR;

    /* program flash */
    while(address < FMC_WRITE_END_ADDR){
        fmc_word_program(address, data0);
        address += 4;
        fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_WPERR );
    }

    /* lock the main FMC after the program operation */
    fmc_lock();
}
V1.6.0:
void fmc_program(void)
{
    /* unlock the flash program/erase controller */
    fmc_unlock();

    /* clear all pending flags */
    fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_WPERR );

    address = FMC_WRITE_START_ADDR;

    /* program flash */
    while(address < FMC_WRITE_END_ADDR){
        fmc_word_program(address, data0);
        address += 4;
        fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_WPERR );
    }

    /* lock the main FMC after the program operation */
    fmc_lock();
}

_________________________________________________________________________________________________________________________________

______________________Module FWDGT_________________________________________________________________________________________________
Fix file:
/fw32103/GD32VW55x_Firmware_Library/Firmware/GD32VW55x_standard_peripheral/Source/gd32vw55x_fwdgt.c
/fw32103/GD32VW55x_Firmware_Library/Firmware/GD32VW55x_standard_peripheral/Include/gd32vw55x_fwdgt.h

fix reason:
Bug fix. Fix the configuration timing issue of FWDGT. First enable the FWDGT, then write PSC and RLD, and wait for RUD and PUD to clear.

V1.5.0:
/*!
    \brief      configure the FWDGT counter prescaler value
    \param[in]  prescaler_value: specify prescaler value
                only one parameter can be selected which is shown as below:
      \arg        FWDGT_PSC_DIV4: FWDGT prescaler set to 4
      \arg        FWDGT_PSC_DIV8: FWDGT prescaler set to 8
      \arg        FWDGT_PSC_DIV16: FWDGT prescaler set to 16
      \arg        FWDGT_PSC_DIV32: FWDGT prescaler set to 32
      \arg        FWDGT_PSC_DIV64: FWDGT prescaler set to 64
      \arg        FWDGT_PSC_DIV128: FWDGT prescaler set to 128
      \arg        FWDGT_PSC_DIV256: FWDGT prescaler set to 256
    \param[out] none
    \retval     ErrStatus: ERROR or SUCCESS
    \note       This function includes timeout exit scenarios.
                Modify according to the user's actual usage scenarios.
*/
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value)
{
    uint32_t timeout = FWDGT_PSC_TIMEOUT;
    uint32_t flag_status = RESET;

    /* enable write access to FWDGT_PSC */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* wait until the PUD flag to be reset */
    do{
        flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
    } while((--timeout > (uint32_t)0U) && (RESET != flag_status));

    if(RESET != flag_status){
        return ERROR;
    }

    /* configure FWDGT */
    FWDGT_PSC = (uint32_t)prescaler_value;

    return SUCCESS;
}

/*!
    \brief      configure the FWDGT counter reload value
    \param[in]  reload_value: specify reload value(0x0000 - 0x0FFF)
    \param[out] none
    \retval     ErrStatus: ERROR or SUCCESS
    \note       This function includes timeout exit scenarios.
                Modify according to the user's actual usage scenarios.
*/
ErrStatus fwdgt_reload_value_config(uint16_t reload_value)
{
    uint32_t timeout = FWDGT_RLD_TIMEOUT;
    uint32_t flag_status = RESET;

    /* enable write access to FWDGT_RLD */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* wait until the RUD flag to be reset */
    do{
        flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
    }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));

    if ((uint32_t)RESET != flag_status){
        return ERROR;
    }

    FWDGT_RLD = RLD_RLD(reload_value);

    return SUCCESS;
}

/*!
    \brief      reload the counter of FWDGT
    \param[in]  none
    \param[out] none
    \retval     none
*/
void fwdgt_counter_reload(void)
{
    FWDGT_CTL = FWDGT_KEY_RELOAD;
}

/*!
    \brief      configure counter reload value, and prescaler divider value
    \param[in]  reload_value: specify reload value(0x0000 - 0x0FFF)
    \param[in]  prescaler_div: FWDGT prescaler value
                only one parameter can be selected which is shown as below:
      \arg        FWDGT_PSC_DIV4: FWDGT prescaler set to 4
      \arg        FWDGT_PSC_DIV8: FWDGT prescaler set to 8
      \arg        FWDGT_PSC_DIV16: FWDGT prescaler set to 16
      \arg        FWDGT_PSC_DIV32: FWDGT prescaler set to 32
      \arg        FWDGT_PSC_DIV64: FWDGT prescaler set to 64
      \arg        FWDGT_PSC_DIV128: FWDGT prescaler set to 128
      \arg        FWDGT_PSC_DIV256: FWDGT prescaler set to 256
    \param[out] none
    \retval     ErrStatus: ERROR or SUCCESS
    \note       This function includes timeout exit scenarios.
                Modify according to the user's actual usage scenarios.
*/
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
{
    uint32_t timeout = FWDGT_PSC_TIMEOUT;
    uint32_t flag_status = RESET;

    /* enable write access to FWDGT_PSC,and FWDGT_RLD */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* wait until the PUD flag to be reset */
    do{
        flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
    }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));

    if ((uint32_t)RESET != flag_status){
        return ERROR;
    }

    /* configure FWDGT */
    FWDGT_PSC = (uint32_t)prescaler_div;

    timeout = FWDGT_RLD_TIMEOUT;
    /* wait until the RUD flag to be reset */
    do{
        flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
    }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));

    if ((uint32_t)RESET != flag_status){
        return ERROR;
    }

    FWDGT_RLD = RLD_RLD(reload_value);

    /* reload the counter */
    FWDGT_CTL = FWDGT_KEY_RELOAD;

    return SUCCESS;
}
V1.6.0:
/*!
    \brief      configure the FWDGT counter prescaler value
    \param[in]  prescaler_value: specify prescaler value
                only one parameter can be selected which is shown as below:
      \arg        FWDGT_PSC_DIV4: FWDGT prescaler set to 4
      \arg        FWDGT_PSC_DIV8: FWDGT prescaler set to 8
      \arg        FWDGT_PSC_DIV16: FWDGT prescaler set to 16
      \arg        FWDGT_PSC_DIV32: FWDGT prescaler set to 32
      \arg        FWDGT_PSC_DIV64: FWDGT prescaler set to 64
      \arg        FWDGT_PSC_DIV128: FWDGT prescaler set to 128
      \arg        FWDGT_PSC_DIV256: FWDGT prescaler set to 256
    \param[out] none
    \retval     ErrStatus: ERROR or SUCCESS
    \note       This function includes timeout exit scenarios.
                Modify according to the user's actual usage scenarios.
*/
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value)
{
    uint32_t timeout = FWDGT_PSC_TIMEOUT;
    uint32_t flag_status;
    ErrStatus status = SUCCESS;

    /* enable write access to FWDGT_PSC */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* configure FWDGT_PSC */
    FWDGT_PSC = (uint32_t)prescaler_value;

    /* wait until the PUD flag to be reset */
    do {
        flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
    } while((--timeout > 0U) && (0U != flag_status));

    if(0U != flag_status) {
        status = ERROR;
    }

    return status;
}

/*!
    \brief      configure the FWDGT counter reload value
    \param[in]  reload_value: specify reload value(0x0000 - 0x0FFF)
    \param[out] none
    \retval     ErrStatus: ERROR or SUCCESS
    \note       This function includes timeout exit scenarios.
                Modify according to the user's actual usage scenarios.
*/
ErrStatus fwdgt_reload_value_config(uint16_t reload_value)
{
    uint32_t timeout = FWDGT_RLD_TIMEOUT;
    uint32_t flag_status;
    ErrStatus status = SUCCESS;

    /* enable write access to FWDGT_RLD */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* configure FWDGT_RLD */
    FWDGT_RLD = RLD_RLD(reload_value);

    /* wait until the RUD flag to be reset */
    do {
        flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
    } while((--timeout > 0U) && (0U != flag_status));

    if(0U != flag_status) {
        status = ERROR;
    }

    return status;
}

/*!
    \brief      reload the counter of FWDGT
    \param[in]  none
    \param[out] none
    \retval     none
*/
void fwdgt_counter_reload(void)
{
    FWDGT_CTL = FWDGT_KEY_RELOAD;
}

/*!
    \brief      configure counter reload value, and prescaler divider value
    \param[in]  reload_value: specify reload value(0x0000 - 0x0FFF)
    \param[in]  prescaler_value: FWDGT prescaler value
                only one parameter can be selected which is shown as below:
      \arg        FWDGT_PSC_DIV4: FWDGT prescaler set to 4
      \arg        FWDGT_PSC_DIV8: FWDGT prescaler set to 8
      \arg        FWDGT_PSC_DIV16: FWDGT prescaler set to 16
      \arg        FWDGT_PSC_DIV32: FWDGT prescaler set to 32
      \arg        FWDGT_PSC_DIV64: FWDGT prescaler set to 64
      \arg        FWDGT_PSC_DIV128: FWDGT prescaler set to 128
      \arg        FWDGT_PSC_DIV256: FWDGT prescaler set to 256
    \param[out] none
    \retval     ErrStatus: ERROR or SUCCESS
    \note       This function includes timeout exit scenarios.
                Modify according to the user's actual usage scenarios.
*/
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_value)
{
    uint32_t timeout = FWDGT_PSC_TIMEOUT;
    uint32_t flag_status;
    ErrStatus status = SUCCESS;

    /* start the free watchdog timer counter */
    FWDGT_CTL = FWDGT_KEY_ENABLE;

    /* enable write access to FWDGT_PSC,and FWDGT_RLD */
    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;

    /* configure FWDGT_PSC */
    FWDGT_PSC = (uint32_t)prescaler_value;

    do {
        flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
    } while((--timeout > 0U) && (0U != flag_status));

    if(0U != flag_status) {
        status = ERROR;
    }

    if(SUCCESS == status) {
        /* configure FWDGT_RLD */
        FWDGT_RLD = RLD_RLD(reload_value);

        /* wait until the RUD flag to be reset */
        timeout = FWDGT_RLD_TIMEOUT;
        do {
            flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
        } while((--timeout > 0U) && (0U != flag_status));

        if(0U != flag_status) {
            status = ERROR;
        }
    }

    if(SUCCESS == status) {
        /* reload the counter */
        FWDGT_CTL = FWDGT_KEY_RELOAD;
    }

    return status;
}
_________________________________________________________________________________________________________________________________

______________________Module QSPI_________________________________________________________________________________________________
Fix file:
/fw32103/GD32VW55x_Firmware_Library/Firmware/GD32VW55x_standard_peripheral/Source/gd32vw55x_qspi.c
/fw32103/GD32VW55x_Firmware_Library/Firmware/GD32VW55x_standard_peripheral/Include/gd32vw55x_qspi.h

fix reason:
Add function. Add void qspi_data_length_config(uint32_t dtlen) API.
V1.5.0:
none
V1.6.0:
/*!
    \brief      configure QSPI data length
    \param[in]  dtlen: 1 ~ 4294967295 (4G-1)
                Please note that when using this function, the parameter passed in is the actual number of data bytes to be transmitted.
    \param[out] none
    \retval     none
*/
void qspi_data_length_config(uint32_t dtlen)
{
    if(dtlen >= 1U){
        QSPI_DTLEN = (dtlen - 1U);
    }else {
        /* do nothing */
    }
}

/fw32103/GD32VW55x_Firmware_Library/Examples/QSPI/Flash_write_read/main.c

fix reason:
Add function. Add void qspi_data_length_config(uint32_t dtlen) API.

V1.5.0:
    QSPI_DTLEN = BUF_SIZE - 1;
V1.5.0:
    qspi_data_length_config(BUF_SIZE);
_________________________________________________________________________________________________________________________________

______________________Module CAU_________________________________________________________________________________________________
Fix file:
/fw32103/GD32VW55x_Firmware_Library/Examples/CAU/CAU_AESECB_mode/main.c
/fw32103/GD32VW55x_Firmware_Library/Examples/CAU/CAU_AES_GCM_CCM_CFB_OFB_mode/main.c
/fw32103/GD32VW55x_Firmware_Library/Examples/CAU/CAU_AES_modes/main.c
/fw32103/GD32VW55x_Firmware_Library/Examples/CAU/CAU_DES_TDES_modes/main.c
/fw32103/GD32VW55x_Firmware_Library/Examples/CAU/CAU_TDESECB_mode/main.c
/fw32103/GD32VW55x_Firmware_Library/Examples/HAU/Hash_SHA1_MD5/main.c
/fw32103/GD32VW55x_Firmware_Library/Examples/HAU/Hash_SHA1_MD5_dma/main.c
/fw32103/GD32VW55x_Firmware_Library/Examples/HAU/Hash_SHA224_SHA256_dma/main.c
/fw32103/GD32VW55x_Firmware_Library/Examples/HAU/Hash_dma_context_switch/main.c
/fw32103/GD32VW55x_Firmware_Library/Examples/HAU/Hmac_SHA1_MD5/main.c
/fw32103/GD32VW55x_Firmware_Library/Examples/HAU/Hmac_SHA224_SHA256_multibuffer_dma/main.c
/fw32103/GD32VW55x_Firmware_Library/Examples/HAU/Hmac_dma_context_switch/main.c

fix reason:
Bug fix.  Use UART transmission functions instead of the printf function to adapt to multiple compilers.


******************* V1.5.0 2025-08-08 ************************************************************************************
______________________Common______________________________________________________________________________________________
Fix file:
..\Firmware\GD32VW55x_standard_peripheral\gd32vw55x.h
fix reason:
update firmware library version get
V1.4.0:
#define __GD32VW55X_STDPERIPH_VERSION_SUB1   (0x04) /*!< [23:16] sub1 version */
V1.5.0:
#define __GD32VW55X_STDPERIPH_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */

Fix file:
..\Firmware\GD32VW55x_standard_peripheral
fix reason:
add corresponding notes to module driver functions with infinite loops or timeout exit mechanisms,
include CAU\EFUSE\FMC\FWDGT\HAU\PKCAU\QSPI\RCU\RTC modules.
V1.4.0:
none
V1.5.0:
    \note       This function includes timeout exit scenarios.
                Modify according to the user's actual usage scenarios.
                This function contains scenarios leading to an infinite loop.
                Modify according to the user's actual usage scenarios.

_________________________________________________________________________________________________________________________________

______________________Module I2C_________________________________________________________________________________________________
Fix file:
../Firmware/GD32VW55x_standard_peripheral/Source/gd32vw55x_i2c.c
../Firmware/GD32VW55x_standard_peripheral/Source/gd32vw55x_i2c.h

fix reason:
bug fix. NACKEN does not support clearing by software. Delete void i2c_nack_disable(uint32_t i2c_periph) API interface

V1.4.0:
/*!
    \brief      generate an ACK in slave mode
    \param[in]  i2c_periph: I2Cx(x=0,1)
    \param[out] none
    \retval     none
*/
void i2c_nack_disable(uint32_t i2c_periph)
{
    I2C_CTL1(i2c_periph) &= ~I2C_CTL1_NACKEN;
}
V1.5.0:
none

Fix file:
../Firmware/GD32VW55x_standard_peripheral/Source/gd32vw55x_i2c.c
../Firmware/GD32VW55x_standard_peripheral/Source/gd32vw55x_i2c.h

fix reason:
Optimize software. Modify the API interface from void i2c_transfer_byte_number_config(uint32_t i2c_periph, uint32_t byte_number)
to void i2c_transfer_byte_number_config(uint32_t i2c_periph, uint8_t byte_number)

V1.4.0:
void i2c_transfer_byte_number_config(uint32_t i2c_periph, uint32_t byte_number)
{
    I2C_CTL1(i2c_periph) &= (uint32_t)(~I2C_CTL1_BYTENUM);
    I2C_CTL1(i2c_periph) |= (uint32_t)(byte_number << CTL1_BYTENUM_OFFSET);
}
V1.5.0:
void i2c_transfer_byte_number_config(uint32_t i2c_periph, uint8_t byte_number)
{
    I2C_CTL1(i2c_periph) &= (uint32_t)(~I2C_CTL1_BYTENUM);
    I2C_CTL1(i2c_periph) |= (uint32_t)((uint32_t)byte_number << CTL1_BYTENUM_OFFSET);
}
_________________________________________________________________________________________________________________________________

______________________Module USART_________________________________________________________________________________________________
Fix file:
../Examples/USART/Half_duplex_transmitter&receiver/main.c

fix reason:
Optimize software. Configure the TX pin from push-pull mode to open-drain mode.
V1.4.0:
    /* configure USART0 Tx as alternate function push-pull */
    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_15);
    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, GPIO_PIN_15);
    /* configure UART1 Tx as alternate function push-pull */
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_2);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, GPIO_PIN_2);
V1.5.0:
    /* configure USART0 Tx as alternate function open drain */
    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_15);
    gpio_output_options_set(GPIOB, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ, GPIO_PIN_15);
    /* configure UART1 Tx as alternate function open drain */
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_2);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ, GPIO_PIN_2);
_________________________________________________________________________________________________________________________________

______________________Module ADC_________________________________________________________________________________________________
Fix file:
../Examples/ADC/Oversample_shift/main.c

fix reason:
Optimize software. Delete oversample configuration.
V1.4.0:
    while(1){
        /* ADC resolusion 12B */
        printf("\r\n resolusion 12B:\r\n");
        adc_resolution_config(ADC_RESOLUTION_12B);
        adc_oversample_mode_config(ADC_OVERSAMPLING_ALL_CONVERT,ADC_OVERSAMPLING_SHIFT_NONE,ADC_OVERSAMPLING_SHIFT_NONE);
        adc_oversample_mode_disable();
        /* 1 time sample */
        adc_enable();
        adc_software_trigger_enable(ADC_ROUTINE_CHANNEL);
        while(RESET == adc_flag_get(ADC_FLAG_EOC));
        delay_1ms(500);
        printf(" 1 time sample,the data is %d\r\n",ADC_RDATA);
        adc_disable();

        /* 16 times sample ,no shift */
        adc_oversample_mode_config(ADC_OVERSAMPLING_ALL_CONVERT,ADC_OVERSAMPLING_SHIFT_NONE,ADC_OVERSAMPLING_RATIO_MUL16);
        adc_oversample_mode_enable();
        adc_enable();
        adc_software_trigger_enable(ADC_ROUTINE_CHANNEL);
        while(RESET == adc_flag_get(ADC_FLAG_EOC));
        delay_1ms(500);
        printf(" 16 times sample,no shift,the data is %d\r\n",ADC_RDATA);
        adc_disable();

        /* 16 times sample ,4 bits shift */
        adc_oversample_mode_config(ADC_OVERSAMPLING_ALL_CONVERT,ADC_OVERSAMPLING_SHIFT_4B,ADC_OVERSAMPLING_RATIO_MUL16);
        adc_enable();
        adc_software_trigger_enable(ADC_ROUTINE_CHANNEL);
        while(RESET == adc_flag_get(ADC_FLAG_EOC));
        delay_1ms(500);
        printf(" 16 times sample,4 bits shift,the data is %d\r\n",ADC_RDATA);
        adc_disable();

        /* ADC resolusion 6B */
        printf("\r\n resolusion 6B:\r\n");
        adc_resolution_config(ADC_RESOLUTION_6B);
        adc_oversample_mode_config(ADC_OVERSAMPLING_ALL_CONVERT,ADC_OVERSAMPLING_SHIFT_NONE,ADC_OVERSAMPLING_SHIFT_NONE);
        adc_oversample_mode_disable();
        /* 1 time sample */
        adc_enable();
        adc_software_trigger_enable(ADC_ROUTINE_CHANNEL);
        while(RESET == adc_flag_get(ADC_FLAG_EOC));
        delay_1ms(500);
        printf(" 1 time sample,the data is %d\r\n",ADC_RDATA);
        adc_disable();

        /* 16 times sample ,no shift */
        adc_oversample_mode_config(ADC_OVERSAMPLING_ALL_CONVERT,ADC_OVERSAMPLING_SHIFT_NONE,ADC_OVERSAMPLING_RATIO_MUL16);
        adc_oversample_mode_enable();
        adc_enable();
        adc_software_trigger_enable(ADC_ROUTINE_CHANNEL);
        while(RESET == adc_flag_get(ADC_FLAG_EOC));
        delay_1ms(500);
        printf(" 16 times sample,no shift,the data is %d\r\n",ADC_RDATA);
        adc_disable();

        /* 16 times sample ,4 bits shift */
        adc_oversample_mode_config(ADC_OVERSAMPLING_ALL_CONVERT,ADC_OVERSAMPLING_SHIFT_4B,ADC_OVERSAMPLING_RATIO_MUL16);
        adc_enable();
        adc_software_trigger_enable(ADC_ROUTINE_CHANNEL);
        while(RESET == adc_flag_get(ADC_FLAG_EOC));
        delay_1ms(500);
        printf(" 16 times sample,4 bits shift,the data is %d\r\n",ADC_RDATA);
        adc_disable();
    }
V1.5.0:
    while(1){
        /* ADC resolusion 12B */
        printf("\r\n resolusion 12B:\r\n");
        adc_resolution_config(ADC_RESOLUTION_12B);
        adc_oversample_mode_disable();
        /* 1 time sample */
        adc_enable();
        adc_software_trigger_enable(ADC_ROUTINE_CHANNEL);
        while(RESET == adc_flag_get(ADC_FLAG_EOC));
        delay_1ms(500);
        printf(" oversample disable,the data is %d\r\n",ADC_RDATA);
        adc_disable();

        /* 16 times sample ,no shift */
        adc_oversample_mode_config(ADC_OVERSAMPLING_ALL_CONVERT,ADC_OVERSAMPLING_SHIFT_NONE,ADC_OVERSAMPLING_RATIO_MUL16);
        adc_oversample_mode_enable();
        adc_enable();
        adc_software_trigger_enable(ADC_ROUTINE_CHANNEL);
        while(RESET == adc_flag_get(ADC_FLAG_EOC));
        delay_1ms(500);
        printf(" 16 times sample,no shift,the data is %d\r\n",ADC_RDATA);
        adc_disable();

        /* 16 times sample ,4 bits shift */
        adc_oversample_mode_config(ADC_OVERSAMPLING_ALL_CONVERT,ADC_OVERSAMPLING_SHIFT_4B,ADC_OVERSAMPLING_RATIO_MUL16);
        adc_enable();
        adc_software_trigger_enable(ADC_ROUTINE_CHANNEL);
        while(RESET == adc_flag_get(ADC_FLAG_EOC));
        delay_1ms(500);
        printf(" 16 times sample,4 bits shift,the data is %d\r\n",ADC_RDATA);
        adc_disable();

        /* ADC resolusion 6B */
        printf("\r\n resolusion 6B:\r\n");
        adc_resolution_config(ADC_RESOLUTION_6B);
        adc_oversample_mode_disable();
        /* 1 time sample */
        adc_enable();
        adc_software_trigger_enable(ADC_ROUTINE_CHANNEL);
        while(RESET == adc_flag_get(ADC_FLAG_EOC));
        delay_1ms(500);
        printf(" oversample disable,the data is %d\r\n",ADC_RDATA);
        adc_disable();

        /* 16 times sample ,no shift */
        adc_oversample_mode_config(ADC_OVERSAMPLING_ALL_CONVERT,ADC_OVERSAMPLING_SHIFT_NONE,ADC_OVERSAMPLING_RATIO_MUL16);
        adc_oversample_mode_enable();
        adc_enable();
        adc_software_trigger_enable(ADC_ROUTINE_CHANNEL);
        while(RESET == adc_flag_get(ADC_FLAG_EOC));
        delay_1ms(500);
        printf(" 16 times sample,no shift,the data is %d\r\n",ADC_RDATA);
        adc_disable();

        /* 16 times sample ,4 bits shift */
        adc_oversample_mode_config(ADC_OVERSAMPLING_ALL_CONVERT,ADC_OVERSAMPLING_SHIFT_4B,ADC_OVERSAMPLING_RATIO_MUL16);
        adc_enable();
        adc_software_trigger_enable(ADC_ROUTINE_CHANNEL);
        while(RESET == adc_flag_get(ADC_FLAG_EOC));
        delay_1ms(500);
        printf(" 16 times sample,4 bits shift,the data is %d\r\n",ADC_RDATA);
        adc_disable();
    }
_________________________________________________________________________________________________________________________

******************* V1.4.0 2025-01-16 ************************************************************************************
______________________Common______________________________________________________________________________________________
Fix file:
..\Firmware\GD32VW55x_standard_peripheral\gd32vw55x.h
fix reason:
add the function to enable the __RISCV_FEATURE_DSP feature macro.
V1.3.0:
none
V1.4.0:
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
#define __RISCV_FEATURE_DSP       1
#endif

Fix file:
..\Firmware\GD32VW55x_standard_peripheral\gd32vw55x.h
fix reason:
update firmware library version get
V1.3.0:
#define __GD32VW55X_STDPERIPH_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
V1.4.0:
#define __GD32VW55X_STDPERIPH_VERSION_SUB1   (0x04) /*!< [23:16] sub1 version */

Fix file:
..\Firmware\GD32VW55x_standard_peripheral\system_gd32vw55x.c
fix reason:
Optimize software frequency-switching patch
V1.3.0:
#define RCU_MODIFY(__delay)     do{                                     \
                                    volatile uint32_t i;                \
                                    if(0 != __delay){                   \
                                        RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                        RCU_CFG0 |= RCU_AHB_CKSYS_DIV4; \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                    }                                   \
                                }while(0)
V1.4.0:
/* The following is to prevent Vcore fluctuations caused by frequency switching. 
   It is strongly recommended to include it to avoid issues caused by self-removal. */
#define RCU_MODIFY(__delay)     do{                                     \
                                    volatile uint32_t i,reg;            \
                                    if(0 != __delay){                   \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                        reg = RCU_CFG0;                 \
                                        reg &= ~(RCU_AHB_CKSYS_DIV2);   \
                                        reg |= RCU_AHB_CKSYS_DIV2;      \
                                        /* AHB = SYSCLK/2 */            \
                                        RCU_CFG0 = reg;                 \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                        reg = RCU_CFG0;                 \
                                        reg &= ~(RCU_AHB_CKSYS_DIV4);   \
                                        reg |= RCU_AHB_CKSYS_DIV4;      \
                                        /* AHB = SYSCLK/4 */            \
                                        RCU_CFG0 = reg;                 \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                    }                                   \
                                }while(0)

Fix file:
..\Firmware\GD32VW55x_standard_peripheral\system_gd32vw55x.c
fix reason:
Add _soft_delay_ function to optimize software frequency-switching patch
V1.3.0:
    RCU_CFG0 &= ~RCU_CFG0_SCS;
V1.4.0:
/* software delay to prevent the impact of Vcore fluctuations.
   It is strongly recommended to include it to avoid issues caused by self-removal. */
static void _soft_delay_(uint32_t time)
{
    __IO uint32_t i;
    for(i=0; i<time*10; i++){
    }
}

    RCU_CFG0 &= ~RCU_CFG0_SCS;
    _soft_delay_(200);

Fix file:
..\Firmware\GD32VW55x_standard_peripheral\system_gd32vw55x.c
fix reason:
Code optimization. Add a condition to execute the frequency-switching patch only when the current clock is PLL.
V1.3.0:
    RCU_MODIFY(0x50);

    RCU_CFG0 &= ~RCU_CFG0_SCS;
V1.4.0:
    if(((RCU_CFG0 & RCU_CFG0_SCSS) == RCU_SCSS_PLLDIG)){
        RCU_MODIFY(0x50);
    }

Fix file:
..\Firmware\GD32VW55x_standard_peripheral\system_gd32vw55x.c
fix reason:
Change the operation mode of the RCU_CFG0 register to read-modify-write.
V1.3.0:
    /* select IRC16M as system clock */
    RCU_CFG0 &= ~RCU_CFG0_SCS;
    RCU_CFG0 |= RCU_CKSYSSRC_IRC16M;
V1.4.0:
    reg_temp = RCU_CFG0;
    /* select IRC16M as system clock */
    reg_temp &= ~RCU_CFG0_SCS;
    reg_temp |= RCU_CKSYSSRC_IRC16M;
    RCU_CFG0 = reg_temp;

Fix file:
..\Firmware\GD32VW55x_standard_peripheral\system_gd32vw55x.c
fix reason:
Change the operation mode of the RCU_CFG0 register to read-modify-write.
V1.3.0:
    /* select HXTAL as system clock */
    RCU_CFG0 &= ~RCU_CFG0_SCS;
    RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
V1.4.0:
    reg_temp = RCU_CFG0;
    /* select HXTAL as system clock */
    reg_temp &= ~RCU_CFG0_SCS;
    reg_temp |= RCU_CKSYSSRC_HXTAL;
    RCU_CFG0 = reg_temp;

Fix file:
..\Firmware\GD32VW55x_standard_peripheral\system_gd32vw55x.c
fix reason:
Change the operation mode of the RCU_CFG0 register to read-modify-write.
V1.3.0:
    /* select PLLDIG as system clock */
    RCU_CFG0 &= ~RCU_CFG0_SCS;
    RCU_CFG0 |= RCU_CKSYSSRC_PLLDIG;
V1.4.0:
    reg_temp = RCU_CFG0;
    /* select PLLDIG as system clock */
    reg_temp &= ~RCU_CFG0_SCS;
    reg_temp |= RCU_CKSYSSRC_PLLDIG;
    RCU_CFG0 = reg_temp;
_________________________________________________________________________________________________________________________________

______________________Module RCU_________________________________________________________________________________________________
Fix file:
..\Examples\RCU\System_clock_switch\main.c
fix reason:
Add RCU_MODIFY(__delay) macro and _soft_delay_ function to optimize System_clock_switch example.
V1.3.0:
none
V1.4.0:
/* The following is to prevent Vcore fluctuations caused by frequency switching. 
   It is strongly recommended to include it to avoid issues caused by self-removal. */
#define RCU_MODIFY(__delay)     do{                                     \
                                    volatile uint32_t i,reg;            \
                                    if(0 != __delay){                   \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                        reg = RCU_CFG0;                 \
                                        reg &= ~(RCU_AHB_CKSYS_DIV2);   \
                                        reg |= RCU_AHB_CKSYS_DIV2;      \
                                        /* AHB = SYSCLK/2 */            \
                                        RCU_CFG0 = reg;                 \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                        reg = RCU_CFG0;                 \
                                        reg &= ~(RCU_AHB_CKSYS_DIV4);   \
                                        reg |= RCU_AHB_CKSYS_DIV4;      \
                                        /* AHB = SYSCLK/4 */            \
                                        RCU_CFG0 = reg;                 \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                    }                                   \
                                }while(0)

/* software delay to prevent the impact of Vcore fluctuations.
   It is strongly recommended to include it to avoid issues caused by self-removal. */
static void _soft_delay_(uint32_t time)
{
    __IO uint32_t i;
    for(i=0; i<time*10; i++){
    }
}

Fix file:
..\Examples\RCU\System_clock_switch\main.c
fix reason:
Add RCU_MODIFY(__delay) macro and _soft_delay_ function to optimize System_clock_switch example.
V1.3.0:
    /* select IRC16M as system clock source, deinitialize the RCU */
    rcu_system_clock_source_config(RCU_CKSYSSRC_IRC16M);
V1.4.0:
    /* It is strongly recommended to use it to avoid issues caused by self-removal. */
    RCU_MODIFY(0x50);
    /* select IRC16M as system clock source, deinitialize the RCU */
    rcu_system_clock_source_config(RCU_CKSYSSRC_IRC16M);
    /* It is strongly recommended to use it to avoid issues caused by self-removal. */
    _soft_delay_(200);

Fix file:
..\Examples\RCU\System_clock_switch\main.c
fix reason:
Add RCU_MODIFY(__delay) macro and _soft_delay_ function to optimize System_clock_switch example.
V1.3.0:
    rcu_system_clock_source_config(RCU_CKSYSSRC_IRC16M);
V1.4.0:
    /* It is strongly recommended to use it to avoid issues caused by self-removal. */
    RCU_MODIFY(0x50);
    rcu_system_clock_source_config(RCU_CKSYSSRC_IRC16M);
    /* It is strongly recommended to use it to avoid issues caused by self-removal. */
    _soft_delay_(200);
_________________________________________________________________________________________________________________________


******************* V1.3.0 2024-07-29 ************************************************************************************
______________________Common______________________________________________________________________________________________
Fix file:
..\Template\main.c
fix reason:
add firmware library version get
V1.2.0:
none
V1.3.0:
#ifdef __FIRMWARE_VERSION_DEFINE
    uint32_t fw_ver = 0;
#endif /* __FIRMWARE_VERSION_DEFINE */

#ifdef __FIRMWARE_VERSION_DEFINE
    fw_ver = gd32vw55x_firmware_version_get();
    /* print firmware version */
    printf("\r\nGD32VW55X series firmware version: V%d.%d.%d", (uint8_t)(fw_ver >> 24), (uint8_t)(fw_ver >> 16), (uint8_t)(fw_ver >> 8));
#endif /* __FIRMWARE_VERSION_DEFINE */

Fix file:
..\Firmware\GD32VW55x_standard_peripheral\system_gd32vw55x.h
fix reason:
add firmware library version get
V1.2.0:
none
V1.3.0:
/* firmware version can be aquired by uncommenting the macro */
#define __FIRMWARE_VERSION_DEFINE

#ifdef __FIRMWARE_VERSION_DEFINE
/* get firmware version */
extern uint32_t gd32vw55x_firmware_version_get(void);
#endif /* __FIRMWARE_VERSION_DEFINE */

Fix file:
..\Firmware\GD32VW55x_standard_peripheral\system_gd32vw55x.c
fix reason:
add firmware library version get
V1.2.0:
none
V1.3.0:
#ifdef __FIRMWARE_VERSION_DEFINE
/*!
    \brief      get firmware version
    \param[in]  none
    \param[out] none
    \retval     firmware version
*/
uint32_t gd32vw55x_firmware_version_get(void)
{
    return __GD32VW55X_STDPERIPH_VERSION;
}
#endif /* __FIRMWARE_VERSION_DEFINE */

Fix file:
..\Firmware\GD32VW55x_standard_peripheral\gd32vw55x.h
fix reason:
update the firmware library version
V1.2.0:
#define __GD32VW55X_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
#define __GD32VW55X_STDPERIPH_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
#define __GD32VW55X_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
V1.3.0:
#define __GD32VW55X_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
#define __GD32VW55X_STDPERIPH_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
#define __GD32VW55X_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */

Fix file:
..\Docs\Schematic
fix reason:
update the schematic
V1.2.0:
GD32VW553H-EVAL-V1.1
V1.3.0:
GD32VW553H-EVAL-V1.2
_________________________________________________________________________________________________________________________________

______________________Module CAU_________________________________________________________________________________________________
Fix file:
..\Firmware\GD32VW55x_standard_peripheral\Source\gd32vw55x_cau.h
fix reason: 
resolve errors in the cau_flag_get function when getting the CAU_FLAG_INFIFO and CAU_FLAG_OUTFIFO flags.
V1.2.0:
#define CAU_FLAG_INFIFO             CAU_STAT1_ISTA                             /*!< IN FIFO flag status */
#define CAU_FLAG_OUTFIFO            CAU_STAT1_OSTA                             /*!< OUT FIFO flag status */
V1.3.0:
#define CAU_FLAG_INFIFO             (CAU_STAT1_ISTA | BIT(31))                 /*!< IN FIFO flag status */
#define CAU_FLAG_OUTFIFO            (CAU_STAT1_OSTA | BIT(31))                 /*!< OUT FIFO flag status */

Fix file:
..\Firmware\GD32VW55x_standard_peripheral\Source\gd32vw55x_cau.c
fix reason: 
resolve errors in the cau_flag_get function when getting the CAU_FLAG_INFIFO and CAU_FLAG_OUTFIFO flags.
V1.2.0:
FlagStatus cau_flag_get(uint32_t flag)
{
    uint32_t reg = 0U;
    FlagStatus ret_flag = RESET;

    /* check if the flag is in CAU_STAT1 register */
    if(RESET != (flag & FLAG_MASK)){
        reg = CAU_STAT1;
    }else{
        /* the flag is in CAU_STAT0 register */
        reg = CAU_STAT0;
    }

    /* check the status of the specified CAU flag */
    if(RESET != (reg & flag)){
        ret_flag = SET;
    }

    return ret_flag;
}
V1.3.0:
FlagStatus cau_flag_get(uint32_t flag)
{
    uint32_t reg = 0U;
    FlagStatus ret_flag = RESET;

    /* check if the flag is in CAU_STAT1 register */
    if(SET == (flag >> 31U)){
        reg = CAU_STAT1;
    } else {
        /* the flag is in CAU_STAT0 register */
        reg = CAU_STAT0;
    }

    /* check the status of the specified CAU flag */
    if(RESET != (reg & flag)){
        ret_flag = SET;
    }

    return ret_flag;
}

Fix file:
..\Firmware\GD32VW55x_standard_peripheral\Source\gd32vw55x_cau_aes.c
fix reason:
code improvement, resolve static test error
V1.2.0:
#define BLOCK_DATA_SIZE   16U
#define MAX_CCM_IV_SIZE   15U

if(ivsize > MAX_CCM_IV_SIZE) {
    return ERROR;
}

V1.3.0:
#define BLOCK_DATA_SIZE   ((uint32_t)0x00000010U)
#define MIN_CCM_IV_SIZE   ((uint32_t)0x00000007U)
#define MAX_CCM_IV_SIZE   ((uint32_t)0x0000000DU)

if((MIN_CCM_IV_SIZE > ivsize) || (MAX_CCM_IV_SIZE < ivsize)) {
    return ERROR;
}

Fix file:
..\Firmware\GD32VW55x_standard_peripheral\Source\gd32vw55x_cau_aes.c
fix reason:
code improvement, resolve static test error
V1.2.0:
    /* read the tag in the OUT FIFO */
    *(uint32_t *)(tagaddr) = cau_data_read();
    tagaddr += 4U;
    *(uint32_t *)(tagaddr) = cau_data_read();
    tagaddr += 4U;
    *(uint32_t *)(tagaddr) = cau_data_read();
    tagaddr += 4U;
    *(uint32_t *)(tagaddr) = cau_data_read();
    tagaddr += 4U;
V1.3.0:
    /* read the tag in the OUT FIFO */
    *(uint32_t *)(tagaddr) = cau_data_read();
    tagaddr += 4U;
    *(uint32_t *)(tagaddr) = cau_data_read();
    tagaddr += 4U;
    *(uint32_t *)(tagaddr) = cau_data_read();
    tagaddr += 4U;
    *(uint32_t *)(tagaddr) = cau_data_read();

Fix file:
..\Firmware\GD32VW55x_standard_peripheral\Source\gd32vw55x_cau_aes.c
fix reason:
code improvement, resolve static test error
V1.2.0:
    if(plen > 4U) {
        /* pad the blockb0 after vectors, and before the last 4 bytes */
        for(i = ivsize; i < 11U; i++) {
            blockb0[i + 1U] = 0U;
        }
        blockb0[12U] = (uint8_t)((inputsize >> 24U) & 0xFFU);
        blockb0[13U] = (uint8_t)((inputsize >> 16U) & 0xFFU);
        blockb0[14U] = (uint8_t)((inputsize >> 8U) & 0xFFU);
        blockb0[15U] = (uint8_t)(inputsize & 0xFFU);
    } else {
        /* the payload length is expressed in plen bytes */
        for(i = ivsize; i < 15U; i++) {
            blockb0[i + 1U] = (uint8_t)((inputsize >> ((plen - 1U) * 8U)) & 0xFFU);
            plen--;
        }
    }
V1.3.0:
    if(plen > 4U) {
        /* pad the blockb0 after vectors, and before the last 4 bytes */
        for(; i < 11U; i++) {
            blockb0[i + 1U] = 0U;
        }
        blockb0[12U] = (uint8_t)((inputsize >> 24U) & 0xFFU);
        blockb0[13U] = (uint8_t)((inputsize >> 16U) & 0xFFU);
        blockb0[14U] = (uint8_t)((inputsize >> 8U) & 0xFFU);
        blockb0[15U] = (uint8_t)(inputsize & 0xFFU);
    } else {
        /* the payload length is expressed in plen bytes */
        for(; i < 15U; i++) {
            blockb0[i + 1U] = (uint8_t)((inputsize >> ((uint8_t)((plen - 1U) * 8U))) & 0xFFU);
            plen--;
        }
    }

Fix file:
..\Examples\CAU\CAU_AES_GCM_CCM_CFB_OFB_mode\main.c
..\Examples\CAU\CAU_AES_modes\main.c
..\Examples\CAU\CAU_AESECB_mode\main.c
..\Examples\CAU\CAU_DES_TDES_modes\main.c
..\Examples\CAU\CAU_TDESECB_mode\main.c
fix reason:
code improvement, add data check function.
V1.2.0:
none
V1.3.0:
    gd_eval_led_init(LED1);

    /* check result */
    if(0U == check_flag) {
        gd_eval_led_on(LED1);
    }

/*!
    \brief      check data in bytes
    \param[in]  src: source
    \param[in]  dst: destination
    \param[in]  len: length of the data to check
    \param[out] none
    \retval     none
*/
void data_check(uint8_t *src, uint8_t *dst, uint32_t len)
{
    if(memcmp((const void *)src, (const void *)dst, len) != 0) {
        check_flag++;
    }
}

Fix file:
..\Examples\CAU\CAU_AES_GCM_CCM_CFB_OFB_mode\main.h
..\Examples\CAU\CAU_AES_GCM_CCM_CFB_OFB_mode\main.c
..\Examples\CAU\CAU_AES_modes\main.h
..\Examples\CAU\CAU_AES_modes\main.c
..\Examples\CAU\CAU_AESECB_mode\main.h
..\Examples\CAU\CAU_AESECB_mode\main.c
..\Examples\CAU\CAU_DES_TDES_modes\main.h
..\Examples\CAU\CAU_DES_TDES_modes\main.c
..\Examples\CAU\CAU_TDESECB_mode\main.h
..\Examples\CAU\CAU_TDESECB_mode\main.c
fix reason:
code improvement
V1.2.0:
put the definitions of keys, vectors and text in main.c
V1.3.0:
add main.h if there is no main.h, modify and move the definitions of keys, vectors and text to main.h.
__________________________________________________________________________________________________________________________

______________________HAU_________________________________________________________________________________________________

Fix file:
..\Examples\HAU\Hmac_SHA224_SHA256_multibuffer_dma\main.c
..\Examples\HAU\Hmac_SHA1_MD5\main.c
..\Examples\HAU\Hmac_dma_context_switch\main.c
..\Examples\HAU\Hash_SHA224_SHA256_dma\main.c
..\Examples\HAU\Hash_SHA1_MD5_dma\main.c
..\Examples\HAU\Hash_SHA1_MD5\main.c
..\Examples\HAU\Hash_dma_context_switch\main.c
fix reason:
code improvement, add data check function.
V1.2.0:
none
V1.3.0:
    gd_eval_led_init(LED1);

    /* check result */
    if(0U == check_flag) {
        gd_eval_led_on(LED1);
    }

/*!
    \brief      check data in bytes
    \param[in]  src: source
    \param[in]  dst: destination
    \param[in]  len: length of the data to check
    \param[out] none
    \retval     none
*/
void data_check(uint8_t *src, uint8_t *dst, uint32_t len)
{
    if(memcmp((const void *)src, (const void *)dst, len) != 0) {
        check_flag++;
    }
}

Fix file:
..\Examples\HAU\Hmac_SHA224_SHA256_multibuffer_dma\main.c
..\Examples\HAU\Hmac_SHA224_SHA256_multibuffer_dma\main.h
..\Examples\HAU\Hmac_SHA1_MD5\main.c
..\Examples\HAU\Hmac_SHA1_MD5\main.h
..\Examples\HAU\Hmac_dma_context_switch\main.c
..\Examples\HAU\Hmac_dma_context_switch\main.h
..\Examples\HAU\Hash_SHA224_SHA256_dma\main.h
..\Examples\HAU\Hash_SHA1_MD5_dma\main.c
..\Examples\HAU\Hash_SHA224_SHA256_dma\main.h
..\Examples\HAU\Hash_SHA1_MD5\main.c
..\Examples\HAU\Hash_SHA1_MD5\main.h
..\Examples\HAU\Hash_dma_context_switch\main.c
..\Examples\HAU\Hash_dma_context_switch\main.h
fix reason:
code improvement
V1.2.0:
put the definitions of keys, message input and expected data in main.c
V1.3.0:
add main.h if there is no main.h, modify and move the definitions of keys, message input and expected data to main.h.
__________________________________________________________________________________________________________________________

______________________QSPI________________________________________________________________________________________________

Fix file:
..\Examples\QSPI\Flash_write_read\main.c

fix reason:
add intermediate process printing
V1.2.0:
int main(void)
{
    uint32_t i = 0;

    gd_eval_com_init(EVAL_COM0);
    /* configure peripheral clock */
    rcu_config();
    /* configure QSPI */
    qspi_flash_init();
    /* qspi flash sector erase */
    qspi_flash_sector_erase();
    /* wait for the BUSY flag to be reset */
    while(RESET != qspi_flag_get(QSPI_FLAG_BUSY)) {
    }
    /* qspi flash program */
    qspi_flash_program();
    /* wait for the BUSY flag to be reset */
    while(RESET != qspi_flag_get(QSPI_FLAG_BUSY)) {
    }
    /* read data by memory map mode */
    qspi_memory_map_read();

    for(i = 0; i < BUF_SIZE; i++) {
        rx_buffer[i] = *(uint8_t *)(0x90000000 + i);
    }

    if(memory_compare(rx_buffer, tx_buffer, BUF_SIZE)) {
        printf("SPI FLASH WRITE AND READ TEST SUCCESS!\r\n");
    } else {
        printf("SPI FLASH WRITE AND READ TEST ERROR!\r\n");
    }
    while(1) {
    }
}
V1.3.0:
int main(void)
{
    uint32_t i = 0;

    gd_eval_com_init(EVAL_COM0);
    /* configure peripheral clock */
    rcu_config();
    printf("QSPI flash writing...\r\n");
    /* configure QSPI */
    qspi_flash_init();
    /* qspi flash sector erase */
    qspi_flash_sector_erase();
    /* wait for the BUSY flag to be reset */
    while(RESET != qspi_flag_get(QSPI_FLAG_BUSY)) {
    }
    /* qspi flash program */
    qspi_flash_program();
    /* wait for the BUSY flag to be reset */
    while(RESET != qspi_flag_get(QSPI_FLAG_BUSY)) {
    }
    printf("QSPI flash reading...\r\n");
    /* read data by memory map mode */
    qspi_memory_map_read();

    for(i = 0; i < BUF_SIZE; i++) {
        rx_buffer[i] = *(uint8_t *)(0x90000000 + i);
    }

    if(memory_compare(rx_buffer, tx_buffer, BUF_SIZE)) {
        printf("SPI FLASH WRITE AND READ TEST SUCCESS!\r\n");
    } else {
        printf("SPI FLASH WRITE AND READ TEST ERROR!\r\n");
    }
    while(1) {
    }
}

__________________________________________________________________________________________________________________________

______________________USART_______________________________________________________________________________________________

Fix file:
..\Examples\USART\DMA_transmitter&receiver_interrupt\main.c
fix reason:
fixed the issue that RXbuffer array will be sent several extra characters when printing with printf in SES environment.
Modify the printf function usart_data_transmit function.
V1.2.0:
    printf("\n\r%s\n\r", rxbuffer);
V1.3.0:
    while(transfersize--){
        while(RESET == usart_flag_get(USART0, USART_FLAG_TBE));
        usart_data_transmit(USART0, rxbuffer[txcount0++]);
    }

__________________________________________________________________________________________________________________________
